Optimized FPGA Implementation of Round-Based Ciphers: A High-Performance and Area-Efficient AES Implementation

Abstract

Modern life relies heavily on embedded systems, which, despite their compact and resource-constrained nature, serve as the core intelligence behind most devices. These smart systems collect user data to continuously decision-making processes. However, the gathered data often includes sensitive information, highlighting the critical need for robust security measures that ensure trustworthiness and reliability without compromising performance. This project aims to identify an optimal implementation technique for security algorithms in embedded systems, balancing resource utilization and timing performance. The primary challenge addressed is maintaining the integrity of the security algorithm while optimizing hardware architecture to maximize . The Rijndael algorithm, specifically the Advanced Encryption Standard (AES), is chosen as the security core and implemented using two distinct techniques. The proposed approach is designed for Field-Programmable Gate Arrays (FPGAs), with results benchmarked against similar projects in terms of timing and area performance.