Optimisations pour la synthèse haut niveau des systèmes embarqués configurables

Abstract

To master the growing complexities of microelectronic systems and to increase productivity, SoC designers should perform modeling, design, synthesis and validation in high levels of abstraction. High Level Synthesis (HLS) provides a good opportunity to overcome the productivity challenges facing embedded systems designers today. The improvement in the qualities of the solutions generated by HLS will lead to promote further its widespread adoption among industry and also in academia. In this thesis we suggested some policies to adopt during the development of an HLS tool to make the generated solutions much more e cient. More speci cally, we proposed strategies enabling the ultimate exploitation of the intrinsic parallelism in algorithms to get high order of improvements in latency and throughput. The often complex interdependence schemes in algorithms limit potentially the ability to acquire ultimate bene ts from intrinsic parallelism. In the present contribution, a compatible C compiler and a code instrumentation module are proposed as a software platform front-end side for parallelism releasing. The dissociation of parallelism is made by conducting explicit discriminations of dependencies in the critical code regions made after the elaboration of Data Flow Graphs (DFG). Our analyzes have led to consider two types of architecture targets for the implementations step, once we have made the transformation and partitioning steps appropriately. We have found appropriate to consider instances of VLIW processors as well as processing units or SIMD Processing Units (PU) for vectorization. The assessment of the intrinsic parallelism in the subset of the CHStone benchmark programs suite is carried out as a validity proof of the robustness of the proposed instrumentation kernel.