Controleur flou testable

Abstract

A 2 Input - 1 Output fuzzy testable controller is designed using a hardware description language "VHDL" on a Xilinx ISE7.1i platform linked to the ModelSim Mentor Graphic simulator. This controller is synthetised as an "IP Core" (Intellectual Property) where testability and speed requirements are strongly exercised. In addition, to get in charge reconfiguration schemes highly targeted by modern applications an architecture is defined. Reported results over of an extensive simulation of the designed controller showed clearly the right strategy and design steps undertaken in this work. The designed controller’s validation has gone through an exhaustive verification phase of all its modules. Experimentation of our controller on a metro braking system is considered. The designed controller constitute the kernel around it we may build up future strategic system commands.